1. Field of the Invention
The present invention generally relates to a method and apparatus that provides dual work function doping and an insulating gate conductor cap that minimizes gate induced drain leakage (GIDL).
2. Description of the Related Art
Over the last several years, significant advances have occurred in increasing the circuit density in integrated circuit chip technology. The ability to provide significantly increased numbers of devices and circuits on an integrated circuit chip has, in turn, created an increased desire to incorporate or integrate additional system functions onto a single integrated circuit chip. In particular, an increasing need exists for joining both memory circuits and logic circuits together on the same integrated circuit chip.
In fabricating dynamic random access memory (DRAM) circuits, the emphasis has been on circuit density along with reduced cost. On the other hand, when fabricating logic circuits, the emphasis has been on creating circuits that operate faster. Accordingly, this desire for dual work function creates additional problems with respect to the complexity and relative cost of the fabricating process. For instance, memory circuits achieve increased density requirements by employing self-aligned contacts (borderless bit line contacts), which are easily implemented in a process having a single type (e.g. typically N+ type) gate work function. A buried-channel P-type metal oxide semiconductor (PMOSFET) is used in creating DRAMs since such permits a single work function gate conductor, N+, to be used throughout the fabrication process. This results in significant cost savings in fabricating DRAMs, but at the expense of creating an inferior performing PMOSFET. On the other hand, logic circuits require both P+ and N+ gated MOSFETs in order to achieve the necessary switching speeds. P+ and N+ gate conductor devices are highly desirable for merged logic and DRAM products.
High-performance logic requires the use of both N+ and P+ doped gate conductors. Although currently practiced high-performance logic processes provide dual workfunction gate conductors, they do not use an insulating gate cap because of density requirements, and hence the need for diffusion contacts borderless to gate conductors, which are of secondary importance to speed. In DRAMs, an insulating cap which is self-aligned to the gate conductor is essential for forming bitline contacts which are borderless to the wordlines. Borderless contacts are needed for achieving the highest density memory cell layouts. However, cost-effective DRAM processes use only a single N+ polysilicon gate conductor. Thus, there is currently no economically attractive process for providing both dual workfunction gate doping and the capability of borderless diffusion contacts.
Furthermore, array device scaling problems (i.e., high well doping that results in high junction leakage and reliability constraints on the maximum wordline boost voltage) makes use of negative wordline-low designs inevitable. Although negative wordline-low designs result in significantly reduced junction area and perimeter leakage and leakage in the depletion region under the gate, gate induced drain leakage (GIDL) is a concern. As is well known in the art, GIDL occurs in the surface depletion region where the wordline overlaps the storage node diffusion and is driven by the field which results from the potential difference between the gate and the diffusion region. Negative wordline-low increases this potential difference. Hence, a method is needed to independently control the thickness of the array region's gate insulator where the gate overlaps the diffusion region without significantly increasing the gate insulator thickness.